Have you got the SPI module configured correctly for phase and polarity? Is the response I have obtained is it right? Did you forget to assert the chip select line? Sign up using Facebook.
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Details are subject to change without notice. Figure 2. Table 1. Figure 3. Figure 4. SPI Modes Supported. Protected Area Sizes. Hold Condition Activation. Block Diagram. Memory Organization. Instruction Set. Status Register Format. Protection Modes. Power-up Timing. Absolute Maximum Ratings. Operating Conditions. AC Measurement Conditions. DC Characteristics. AC Characteristics. Serial Input Timing. Hold Timing. Output Timing. SO16 wide — 16 lead Plastic Small Outline, mils body width.
Ordering Information Scheme. Document Revision History. The memory can be programmed 1 to bytes at a time, using the Page Program instruction.
The memory is organized as sectors, each containing pages. Each page is bytes wide. Thus, the whole memory can be viewed as consisting of pages, or bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.
There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. This output signal is used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial Clock C. Serial Data Input D. This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock C. Serial Clock C. This input signal provides the timing of the serial interface.
Chip Select S. When this input signal is High, the device is deselected and Serial Data Output Q is at high impedance. After Power-up, a falling edge on Chip Select S is required prior to the start of any instruction.
Hold HOLD. The Hold HOLD signal is used to pause any serial communications with the device without deselecting the device.
Write Protect W. The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions as specified by the values in the BP2, BP1 and BP0 bits of the Status Register.
The difference between the two modes, as shown in Figure 6. Figure 6. This is followed by the internal Program cycle of duration tPP. To spread this overhead, the Page Program PP instruction allows up to bytes to be programmed at a time changing bits from 1 to 0 , provided that they lie in consecutive addresses on the same page of memory. Before this can be applied, the bytes of memory need to have been erased to all 1s FFh.
This can be achieved either a sector at a time, using the Sector Erase SE instruction, or throughout the entire memory, using the Bulk Erase BE instruction. The Write In Progress WIP bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
The device then goes in to the Standby Power mode. The device consumption drops to ICC1. Status Register The Status Register contains a number of status and control bits that can be read or set as appropriate by specific instructions. WIP bit. WEL bit. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. No SPI device can operate correctly in the presence of excessive noise.
This bit is returned to its reset state by the following events: Table 2. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. Similarly, if the Figure 7. This is shown in Figure 7. Normally, the device is kept selected, with Chip Select S driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition.
If Chip Select S goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. This prevents the device from going back to the Hold condition. Figure 8. Block Diagram Each page can be individually programmed bits are programmed from 1 to 0. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input D , each bit being latched on the rising edges of Serial Clock C.
The instruction set is listed in Table Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select S can be driven High after any bit of the data-out sequence is being shifted out. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
Figure 9. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte 20h , and the memory capacity of the device in the second byte 17h.
Any Read Identification RDID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select S Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the bit device identification, stored in the memory, being shifted out on Serial Data Output Q , each bit being shifted out during the falling edge of Serial Clock C.
The instruction sequence is shown in Figure Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. When one of these cycles is in progress, it is recommended to check the Write In Progress WIP bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure Table 6. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
Figure Chip Select S must be driven High after the eighth bit of the data byte has been latched in. The protection features of the device are summarized in Table 7. Attempts to write to the Status Register are rejected, and are not accepted for execution.
Then the memory contents, at that address, is shifted out on Serial Data Output Q , each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock C. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely.
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