Voodoobei Datasheets search archive of electronic components datasheets You should see a graph similar to the one shown below in figure cd datasheet. You will see how the voltage transfer curve changes with VDD. Describe the differences between the screenshots other than that they are inverted. There are 6 parts and a bonus. Clean up Previous datashset 7.
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Digital Reader 8. You can download or view the data sheet here or here. Each pair shares a common gate pins 6,3, The other two pairs are more general purpose. Figure 1: CD functional diagram.
The CD is a very versatile IC with many uses. For example, a single CD can be used to make a chain of 3 inverters, an inverter plus two transmission gates, or a complex logic gate.
Inverters and transmission gates are particularly useful for building D flip-flops. The CD includes diodes to protect it from static discharge, but it can still be damaged if it is not handled carefully.
Normally one would use anti-static mats and wrist straps when working with static sensitive electronics. However, we do not have those in the lab. A low budget way to avoid static discharge is to ground yourself before touching an IC. Groups of pins that are not connected are separated by a semicolon. For example, consider 22,5,7 ; 1,3, This notation is often used in datasheets, and is used below as well.
Draw an equivalent circuit for the following wiring description using a CD 1,5,10 ; 3,8,13 ; 14,2,11 ; 7,4,9 ; 14,Vdd ; 7,Ground. You do not have to draw a gate level schematic if you can determine the logic function implemented.
If you only give a logic diagram, show pin numbers between logic elements. Make a pin-level wiring diagram for a transmission gate using a CD Figure 2: CD functional diagram.
Determine the logic function implemented by the following connections to a CD 2,14 ; 8,9,4 ; 12,13,5 ; 1,11 ; 14,Vdd ; 7,Gnd. The output is pin 12,13, or 5. Draw a transistor level diagram and a truth table for the circuit. Set the function generator to output a Hz sine wave, 5vpp, 2.
Remember to ground the AI- terminals. The respective input-output pairs are: ,, You should see 3 waveforms similar to the one shown in figure 3.
Figure 3: Output of first inverter. Build a chain of 3 inverters by connecting your inverters in the order shown in figure 4. Figure 4: Inverter chain. You should take a total of three screenshots, one each, corresponding to each inverter output.
Figure 5: Output of second inverter. Do not dissassemble the inverter chain. It will be reused later. What to do in lab report Show 3 screen shots of inverter outputs.
Describe the differences between the screenshots other than that they are inverted. We will test the two transmission gates by connecting FGEN to the input, and connecting a load of 1k on either output sides. Connect pins 2,9 to CH0, and pins 4,11 to CH1. Remember to ground the CH - terminals.
Figure 6: Double transmission gate connections. Set the function generator to produce a Hz square wave, 5vpp, 2. In each case take a screen-shot. The two transmission gates work in tandem to realize the D-latch. During the transparent phase of the latch, i. D is transmitted to the output Q through the first transmission gate and the two-inverter cascade.
During the hold phase of the latch, i. As a result, any change in the input D is not reflected at the output Q. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed loop with the two-inverter cascade.
Connect pin 9, which serves as D input of the latch to DIO0. Connect pin 4, which serves as Q output of the latch to DIO8. Figure 7: Schematic of D latch. Now insert two inverter chain you built earlier and retained from the first exercise to the circuit you have just built.
It is shown in the dashed box labeled as chip 2 in Figure 7 above. A steady high should appear. Capture a screen shot. Observe the output on DIO8. This is the transparent phase of the latch. You should see that DIO8 is also low. Also apply logic High to the D input.
Observe the DIO8 pin. A steady low should appear inspite of changing D to logic High since the previous value at D-input was low. This is the opaque phase of the latch.
Two copies with opposite phase clocks will then make a master-slave D Flip Flop. That is going to be left as a bonus exercise. A widely used circuit is a master slave D flip flop, which we will build and test below.
We will use the D-latch constructed in the previous section as the master latch in our master slave D flip flop. We will now need to construct another D-latch that will serve as slave latch to form our master-slave D Flip-flop as shown in Figure 8 Click on the Figure to view a full-size picture.
For the complete circuit you will need 4 CD chips. Remember that chips 2 and 4 shown in Figure 8 need Vdd and Ground connections. Proceed as follows: Figure 8: Schematic of D flip flop. Build another set of transmission gates on a third CD chip. For this pair the clock must be inverted, so the wiring is slightly different: 1,5,12 ; 2,9 ; 11,4 ; 3,8,13 ; 6,10 ; 7, ground ; 14, VDD.
Pin 2 or 9 is the D input, pin 4 or 11 is the Q output, and pin 6 is the clock signal. Build a second inverter buffer on a fourth CD chip: 4,7 ; 1,5 ; 3, 8,13 ; 14,2 ; 14,Vdd ; 7,Ground. Pin 6 is the input and pin 1 or 5 is the output. Complete the slave latch by connecting the buffer on chip 4 to the transmission gates on chip 3.
Connect pin 6 on chip 4 to pin 1, 5, or 12 on chip 3. Connect pin 1 or 5 on chip 4 to pin 4 or 11 on chip 3. Test your second latch. Does the output follow the input when the clock is high? Will the latch hold both high and low states when the clock is low? Connect the output of the first latch to the input of the second latch connect pin 4 or 11 on chip 1 to pin 2 or 9 on chip 3.
Tie the clock signals together connect pin 6 on chip 1 to pin 6 on chip 3. This combination is a master-slave flip-flop. Connect clock to FGEN. Connect the D input to the AO0. Connect AI1 to the output. Download the waveform file here. Load the waveform file into the arbitrary waveform generator and check the box the box next to Enabled. Click run. This waveform is the input data. Use the function generator to generate a 5v clock signal 5Vpp, 2. Use the scope to observe the output and clock.
Save a screenshot. Is the flip-flop rising or falling edge triggered? Thank you for keeping our lab clean and organized. Feedback You are encouraged to write down your experience with this lab along with any feedback or suggestions. You can also document mistakes or missteps that occurred, e. Such information will be used to improve this and future labs and your experience will help future students.
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